Peterson's IC Diary

Intro  Welcome to my little website! This is my very first post. On this site I would share some interesting ‘IC-related gadgets’ that I find useful during my current work as a digital verification intern. Stay tuned for my casual scribblings if you’d like! Overview  As a hardware engineer, apart from mastering HDL like Verilog and VerilogA etc., understanding one or two software programming languages of personal preference is also important.  It is agreed that when ...

Digital Verification Fulltext Link  Block Level    Verilog Fulltext Link       Display on Shell      Waveform on Verdilog    Cadence Fulltext Link       ADE-L      VerilogA   Fullchip Level    FPGA Configuration      HqFPGA on Linux      Hq ...

The Code Slicer  When dealing with a large-scale project like this, instinct tells us to split it into “bite-size” pieces. And that’s exactly how we’re gonna begin.  So for starters, I wanna talk about a set of statements in Verilog commonly used as the “slicer” for huge programmes in real practice. 1234`define`ifdef`include`elsif   In this context, typically what “include” does is it extracts the text contained in the .v file and pastes it in the file where the sta ...

(Does anyone know how to get syntax highlight for VerilogA in Markdown…?)Coming Soon…

Coming Soon…

Overview  So we’re looking at a block level digital unit here, which basically means that at a conceptual level conventional methods for testing an uncomplicated electronic device apply on the nose.  As we’ve been taught in digital electronics lectures, there are several ways to describe the logic functions of a digital unit: standard expressions (SOP or POS) and truth table or a sample waveform graph that demonstrates equivalent information.(To keep things simple and easy to ...

Preface  When it comes to verification for FPGA (or basically any VLSI in real practice), we’re often provided with two perspectives: block-level verification which checks the functionality of each component that constitutes the IC chip; and fullchip-level verification which examines the entire workflow of the chip.  Block-level verification resembles conventional simulation for any electronic design in the industry. Meanwhile, in order to perform fullchip verification for an ...

Welcome to Hexo! This is your very first post. Check documentation for more info. If you get any problems when using Hexo, you can find the answer in troubleshooting or you can ask me on GitHub. Quick StartCreate a new post1$ hexo new "My New Post" More info: Writing Run server1$ hexo server More info: Server Generate static files1$ hexo generate More info: Generating Deploy to remote sites1$ hexo deploy More info: Deployment